The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Aug. 09, 2010
Applicants:

Ravindraraj Ramaraju, Round Rock, TX (US);

Kenneth R. Burch, Austin, TX (US);

Charles E. Seaberg, Austin, TX (US);

Inventors:

Ravindraraj Ramaraju, Round Rock, TX (US);

Kenneth R. Burch, Austin, TX (US);

Charles E. Seaberg, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G11C 5/14 (2006.01); G05F 1/577 (2006.01); G05F 1/00 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G05F 1/00 (2013.01); G05F 1/577 (2013.01);
Abstract

Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.


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