The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jul. 11, 2014
Applicant:

Sensus Spectrum Llc, Raleigh, NC (US);

Inventors:

H. Britton Sanderford, Jr., New Orleans, LA (US);

Robert E. Rouquette, Kenner, LA (US);

Gary A. Naden, Mandeville, LA (US);

Marc L. Reed, Mandeville, LA (US);

Gordon J. Boudreaux, Arabi, LA (US);

Michael R. Brown, Mandeville, LA (US);

Assignee:

SENSUS SPECTRUM LLC, Raleigh, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H04L 5/06 (2006.01); H04L 5/16 (2006.01); H04L 25/06 (2006.01); H04L 25/49 (2006.01); H04L 27/12 (2006.01); H04L 27/233 (2006.01); H04L 27/32 (2006.01); H04L 27/34 (2006.01); H04L 27/36 (2006.01); H04L 27/38 (2006.01); H03B 21/00 (2006.01); H04W 36/08 (2009.01); H04W 72/04 (2009.01);
U.S. Cl.
CPC ...
H03L 7/08 (2013.01); H03B 21/00 (2013.01); H04L 5/06 (2013.01); H04L 5/16 (2013.01); H04L 25/061 (2013.01); H04L 25/4902 (2013.01); H04L 25/4921 (2013.01); H04L 27/12 (2013.01); H04L 27/2331 (2013.01); H04L 27/32 (2013.01); H04L 27/34 (2013.01); H04L 27/3433 (2013.01); H04L 27/3483 (2013.01); H04L 27/364 (2013.01); H04L 27/38 (2013.01); H04L 27/3845 (2013.01); H04W 36/08 (2013.01); H04W 72/0426 (2013.01);
Abstract

A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal.


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