The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Apr. 23, 2010
Applicants:

Teruyuki Fujii, Atsugi, JP;

Kohei Ohshima, Atsugi, JP;

Junya Maruyama, Ebina, JP;

Akihisa Shimomura, Atsugi, JP;

Inventors:

Teruyuki Fujii, Atsugi, JP;

Kohei Ohshima, Atsugi, JP;

Junya Maruyama, Ebina, JP;

Akihisa Shimomura, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/0296 (2006.01); H01L 31/02 (2006.01); H01L 31/028 (2006.01); H01L 31/068 (2012.01); H01L 31/075 (2012.01);
U.S. Cl.
CPC ...
H01L 31/022425 (2013.01); H01L 31/0296 (2013.01); H01L 31/028 (2013.01); H01L 31/02008 (2013.01); H01L 31/068 (2013.01); H01L 31/075 (2013.01); Y02E 10/50 (2013.01);
Abstract

An object relates to an electrode of a semiconductor device or a method for manufacturing a semiconductor device, which includes a bonding step, and problems are: (1) high resistance of a semiconductor device due to the use of an Al electrode, (2) formation of an alloy by Al and Si, (3) high resistance of a film formed by a sputtering method, and (4) defective bonding in a bonding step which is caused if a bonding surface has a large unevenness. A semiconductor device includes a metal substrate or a substrate provided with a metal film, a copper (Cu) plating film over and bonded to the metal substrate or the metal film by employing a thermocompression bonding method, a barrier film over the Cu plating film, a single crystal silicon film over the barrier film, and an electrode layer over the single crystal silicon film.


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