Low-leakage, high-capacitance capacitor structures and method of making

Abstract

A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.