The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Feb. 04, 2014
Applicant:

Seiko Instruments Inc., Chiba, JP;

Inventors:

Keisuke Uemura, Chiba, JP;

Jun Osanai, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 23/481 (2013.01); H01L 23/293 (2013.01); H01L 24/05 (2013.01); H01L 2224/02163 (2013.01); H01L 2224/02233 (2013.01); H01L 2224/02255 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01);
Abstract

Provided is a semiconductor device configured to prevent a penetration of moisture into an internal circuit. The moisture from a bonding pad to the internal circuit is blocked by providing an underlying polysilicon film () formed as a lower layer of a bonding pad, a bonding pad () formed above the underlying polysilicon film () through intermediation of an inter-layer insulation film (), and an outer circumferential interconnecting line () formed so as to surround an outer side of the bonding pad, and by connecting the outer circumferential interconnecting line () and the underlying polysilicon film () with a continuous outer circumferential contact.


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