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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9111947 B1

PDFFull Text
Date of Patent:
Aug. 18, 2015

Filed:

Jun. 04, 2013

Chip arrangement with a recessed chip housing region and a method for manufacturing the same

Applicant:

Intel Mobile Communications Gmbh, Neubiberg, DE;

Inventors:

David O'Sullivan, Sinzing, DE;

Thorsten Meyer, Regensburg, DE;

Assignee:

INTEL DEUTSCHLAND GMBH, Neubiberg, DE;

Attorney:
Primary Examiner:

A Sefer

Assistant Examiner:

Dilinh Nguyen

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/28 (2006.01); H01L 23/04 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 23/3157 (2013.01);
Abstract

A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.

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