The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jun. 10, 2008
Applicants:

Mukund P. Khatri, Austin, TX (US);

Vijay Nijhawan, Austin, TX (US);

Dirie N. Herzi, Round Rock, TX (US);

Madhusudhan Rangarajan, Round Rock, TX (US);

Inventors:

Mukund P. Khatri, Austin, TX (US);

Vijay Nijhawan, Austin, TX (US);

Dirie N. Herzi, Round Rock, TX (US);

Madhusudhan Rangarajan, Round Rock, TX (US);

Assignee:

Dell Products, LP, Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/48 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4893 (2013.01); G06F 1/3203 (2013.01); G06F 1/329 (2013.01); G06F 2209/483 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/144 (2013.01);
Abstract

An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.


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