The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jul. 11, 2012
Applicants:

Yusuke Shirota, Kanagawa, JP;

Tetsuro Kimura, Tokyo, JP;

Tatsunori Kanai, Kanagawa, JP;

Haruhiko Toyama, Kanagawa, JP;

Koichi Fujisaki, Kanagawa, JP;

Junichi Segawa, Kanagawa, JP;

Masaya Tarui, Kanagawa, JP;

Satoshi Shirai, Kanagawa, JP;

Hiroyoshi Haruki, Kanagawa, JP;

Akihiro Shibata, Tokyo, JP;

Inventors:

Yusuke Shirota, Kanagawa, JP;

Tetsuro Kimura, Tokyo, JP;

Tatsunori Kanai, Kanagawa, JP;

Haruhiko Toyama, Kanagawa, JP;

Koichi Fujisaki, Kanagawa, JP;

Junichi Segawa, Kanagawa, JP;

Masaya Tarui, Kanagawa, JP;

Satoshi Shirai, Kanagawa, JP;

Hiroyoshi Haruki, Kanagawa, JP;

Akihiro Shibata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3275 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/32 (2013.01);
Abstract

According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.


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