The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Jan. 20, 2015
Applicant:

Newlans, Inc., Acton, MA (US);

Inventors:

Anuj Madan, Cambridge, MA (US);

Dev V. Gupta, Concord, MA (US);

Zhiguo Lai, Acton, MA (US);

Assignee:

NEWLANS, INC., Acton, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 5/00 (2006.01); H01G 5/00 (2006.01); H01G 7/00 (2006.01); G05F 3/16 (2006.01); H01L 27/12 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
G05F 3/16 (2013.01); H01L 27/1203 (2013.01); H01L 29/94 (2013.01);
Abstract

Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.


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