The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Sep. 30, 2014
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Burhan Masood, Irvine, CA (US);

Howard Frazier, Pleasanton, CA (US);

Assignee:

BROADCOM CORPORATION, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/947 (2013.01); H04L 12/761 (2013.01); H04L 12/40 (2006.01); G06F 13/00 (2006.01); H04L 12/931 (2013.01); H04L 12/18 (2006.01); H04L 12/721 (2013.01);
U.S. Cl.
CPC ...
H04L 49/25 (2013.01); G06F 13/00 (2013.01); H04L 12/18 (2013.01); H04L 12/4013 (2013.01); H04L 45/16 (2013.01); H04L 45/44 (2013.01); H04L 49/00 (2013.01); H04L 49/351 (2013.01); Y02B 60/31 (2013.01);
Abstract

Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.


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