The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Jan. 13, 2011
Applicants:

Koichi Shimizu, Tokyo, JP;

Daisuke Suzuki, Tokyo, JP;

Tomomi Kasuya, Tokyo, JP;

Inventors:

Koichi Shimizu, Tokyo, JP;

Daisuke Suzuki, Tokyo, JP;

Tomomi Kasuya, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 9/08 (2006.01); H03K 3/02 (2006.01); H03K 5/1252 (2006.01); H04L 9/32 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 3/02 (2013.01); H03K 5/1252 (2013.01); H03K 19/003 (2013.01); H04L 9/3278 (2013.01); H03K 19/00361 (2013.01);
Abstract

A bit generation apparatus includes a glitch generation circuit that generates glitch signals which include a plurality of pulses, and T-FF bit generation circuits which input the glitch signals, and based on either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate a bit value of either 0 or 1. Each of the T-FF bit generation circuits generates a respective bit value based on either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of employment of the T-FF bit generation circuits, circuits that are conventionally required but not essential for the glitch become unnecessary. This serves to prevent expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit.


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