The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Dec. 11, 2013
Applicant:

Stephen D. Hersee, Summerland Key, FL (US);

Inventor:

Stephen D. Hersee, Summerland Key, FL (US);

Assignee:

STC.UNM, Albuquerque, NM (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/34 (2006.01); H01S 5/343 (2006.01); H01S 5/40 (2006.01); B82Y 20/00 (2011.01);
U.S. Cl.
CPC ...
H01S 5/34333 (2013.01); H01S 5/34 (2013.01); H01S 5/4025 (2013.01); B82Y 20/00 (2013.01); Y10S 977/951 (2013.01);
Abstract

According to various embodiments, the present teachings include an array of nanowire devices. The array of nanowire devices comprises a readout integrated circuit (ROIC). An LED array is disposed on the ROIC. The LED array comprises a plurality of LED core-shell structures, with each LED core-shell structure comprising a layered shell enveloping a nanowire core, wherein the layered shell comprises a multi-quantum-well (MQW) active region. The LED array further comprises a p-side electrode enveloping the layered core-shell structure and electrically connecting the ROIC, wherein each p-side electrode has an average thickness ranging from about 100 nm to about 500 nm. A dielectric layer is disposed on the plurality of LED core-shell structures, with each nanowire core disposed through the dielectric to connect with an n-side semiconductor that is situated on the dielectric.


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