The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2015
Filed:
Dec. 27, 2010
Applicants:
Matthias Hierlemann, Fishkill, NY (US);
Chandrasekhar Sarma, Poughkeepsie, NY (US);
Inventors:
Matthias Hierlemann, Fishkill, NY (US);
Chandrasekhar Sarma, Poughkeepsie, NY (US);
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 21/84 (2013.01); H01L 29/0653 (2013.01); H01L 29/78 (2013.01); H01L 29/7845 (2013.01); H01L 29/7846 (2013.01);
Abstract
A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate including the polycrystalline silicon is then completed.