The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2015
Filed:
Dec. 12, 2013
Applicant:
Cypress Semiconductor Corporation, San Jose, CA (US);
Inventors:
Helmut Puchner, Santa Clara, CA (US);
Igor Polishchuk, Fremont, CA (US);
Sagy Charel Levy, Zichron Yaakov, IL;
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 21/28282 (2013.01); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/66833 (2013.01);
Abstract
A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.