The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2015
Filed:
Mar. 24, 2014
Applicant:
Silanna Semiconductor U.s.a., Inc., San Diego, CA (US);
Inventor:
Stephen A. Fanelli, San Marcos, CA (US);
Assignee:
Silanna Semiconductor U.S.A., Inc., San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/46 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76256 (2013.01); H01L 29/0649 (2013.01); H01L 29/7842 (2013.01);
Abstract
A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC layer as an etch stop. In some embodiments, the SiGeC layer is then removed; but in some other embodiments, it remains as a strain-inducing layer.