The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Nov. 12, 2012
Applicant:

Marvell Israel (M.i.s.l.) Ltd., Yokneam, IL;

Inventor:

Evgeny Shumsky, Petah Tikva, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/16 (2006.01); G06F 13/372 (2006.01); G06F 13/362 (2006.01); G06F 12/08 (2006.01); G06F 12/02 (2006.01); G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/00 (2013.01); G06F 12/0284 (2013.01); G06F 12/0844 (2013.01); G06F 13/14 (2013.01); G06F 13/161 (2013.01); G06F 13/1621 (2013.01); G06F 13/1626 (2013.01); G06F 13/1642 (2013.01); G06F 13/1652 (2013.01); G06F 13/1657 (2013.01); G06F 13/1663 (2013.01); G06F 13/1673 (2013.01); G06F 13/3625 (2013.01); G06F 13/372 (2013.01);
Abstract

Some of the embodiments of the present disclosure provide a multi-core switch device comprising a plurality of P processing cores for processing packets received from a computer network; a memory comprising a plurality of M memory banks, the plurality of processing cores and the plurality of memory banks being arranged such that the plurality of processing cores have access to multiple memory banks among the plurality of memory banks to perform corresponding memory operations; and a memory access controller coupling the plurality of processing cores to the plurality of memory banks, the memory access controller configured to selectively provide, to each of the plurality of processing cores, access to multiple memory banks among the plurality of memory banks over a number of N physical couplings such that N (i) is an integer and (ii) is less than P times M.


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