The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Nov. 05, 2012
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Steven S. Thomson, San Diego, CA (US);

Bohuslav Rychlik, San Diego, CA (US);

Ali Iranli, San Diego, CA (US);

Sumit Sur, Boulder, CO (US);

Norman Scott Gargash, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01); G06F 1/26 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01); G06F 1/26 (2013.01); G06F 1/32 (2013.01); G06F 9/5094 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1285 (2013.01);
Abstract

Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.


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