The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Dec. 23, 2009
Applicants:

Fadi Busaba, Poughkeepsie, NY (US);

Brian Curran, Saugerties, NY (US);

Lee Eisen, Round Rock, TX (US);

Christian Jacobi, Poughkeepsie, NY (US);

David A. Schroter, Round Rock, TX (US);

Eric Schwarz, Gardiner, NY (US);

Inventors:

Fadi Busaba, Poughkeepsie, NY (US);

Brian Curran, Saugerties, NY (US);

Lee Eisen, Round Rock, TX (US);

Christian Jacobi, Poughkeepsie, NY (US);

David A. Schroter, Round Rock, TX (US);

Eric Schwarz, Gardiner, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3017 (2013.01); G06F 9/30043 (2013.01); G06F 9/3836 (2013.01); G06F 9/3867 (2013.01);
Abstract

A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.


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