The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Jun. 30, 2012
Applicants:

David Haase, Fuquay Varina, NC (US);

Michael D. Haynes, Raleigh, NC (US);

Miles A. DE Forest, Bahama, NC (US);

Paul T. Mcgrath, Raleigh, NC (US);

Dayanand Suldhal, New Canaan, CT (US);

Nagapraveen Veeravenkata Seela, Cary, NC (US);

Alan L. Taylor, Cary, NC (US);

Inventors:

David Haase, Fuquay Varina, NC (US);

Michael D. Haynes, Raleigh, NC (US);

Miles A. de Forest, Bahama, NC (US);

Paul T. McGrath, Raleigh, NC (US);

Dayanand Suldhal, New Canaan, CT (US);

Nagapraveen Veeravenkata Seela, Cary, NC (US);

Alan L. Taylor, Cary, NC (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0644 (2013.01); G06F 3/0665 (2013.01); G06F 12/0223 (2013.01); G06F 12/0607 (2013.01);
Abstract

A method, computer program product, and computing system for identifying a target storage device upon which a plurality of logical storage devices are to be defined. The target storage device includes a plurality of physical storage blocks. At least a first logical storage device and a second logical storage device are defined for mapping within the target storage device. Each of the first and second logical storage devices includes a plurality of logical storage slices. At least a portion of the logical storage slices for each of the first and second logical storage devices are non-sequentially mapped to at least a portion of the plurality of physical storage blocks included within the target storage device to generate an interlaced target storage device.


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