The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2015
Filed:
Jun. 01, 2011
Warren J. Gross, Montreal, CA;
Shie Mannor, Haifa, IL;
Saeed Sharifi Tehrani, San Diego, CA (US);
THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY, Montreal, Quebec, CA;
Abstract
A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.