The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9099547 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 04, 2015

Filed:

Dec. 06, 2011
Applicants:

Stefan Martens, Munich, DE;

Mathias Vaupel, Regensburg, DE;

Inventors:

Stefan Martens, Munich, DE;

Mathias Vaupel, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/78 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 22/14 (2013.01);
Abstract

In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies.


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