The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2015

Filed:

Mar. 13, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-Ho Lee, Hwaseong-si, KR;

Jae-Hwang Sim, Seoul, KR;

Sang-Yong Park, Suwon-si, KR;

Kyung-Lyul Moon, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 23/528 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 27/115 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/3086 (2013.01); H01L 21/3088 (2013.01); H01L 21/31144 (2013.01); H01L 21/76229 (2013.01); H01L 21/76816 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 21/76838 (2013.01); H01L 27/10814 (2013.01); H01L 27/10855 (2013.01);
Abstract

Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.


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