The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2015

Filed:

Jun. 28, 2011
Applicants:

Yukio Tsuzuki, Nukata-gun, JP;

Makoto Asai, Kariya, JP;

Inventors:

Yukio Tsuzuki, Nukata-gun, JP;

Makoto Asai, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26586 (2013.01); H01L 29/1095 (2013.01); H01L 29/41766 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7806 (2013.01); H01L 29/7813 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01);
Abstract

A semiconductor device includes an n-conductive type semiconductor substrate having a main side and a rear side, a p-conductive type layer arranged over the main side of the substrate, a main side n-conductive type region arranged in the p-conductive type layer, a rear side n-conductive type layer arranged over the rear side of the substrate, a first trench which reaches the substrate and penetrates the main side n-conductive type region and the p-conductive type layer, a second trench which reaches an inside of the p-conductive type layer, a second electrode layer, which is embedded in the second trench and connected to the p-conductive type layer. Hereby, the semiconductor device, in which the recovery property of a diode cell can be improved without damaging the property of a MOS transistor cell or an IGBT cell and the surge withstand property does not deteriorate, can be obtained.


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