The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2015
Filed:
Mar. 18, 2013
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Sang Yong Lee, Icheon-si, KR;
Si Han Kim, Yongin-si, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H05K 1/18 (2006.01); H05K 3/12 (2006.01); H05K 3/18 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 23/3128 (2013.01); H01L 23/498 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 24/92 (2013.01); H05K 1/185 (2013.01); H01L 24/13 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/214 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82101 (2013.01); H01L 2224/82102 (2013.01); H01L 2224/82104 (2013.01); H01L 2224/82106 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/92 (2013.01); H01L 2224/92132 (2013.01); H01L 2224/92244 (2013.01); H05K 3/12 (2013.01); H05K 3/18 (2013.01); H05K 3/4644 (2013.01);
Abstract
An embedded package in which active elements, such as semiconductor chips, are embedded within a package substrate. The semiconductor chips, embedded within a dielectric layer, are coupled with circuit wires to ensure electrical and signal continuity. When connections between the semiconductor chip and the package substrate are performed in different directions, there is a reduction in overall interconnection area, connection reliability is improved, leakage currents are reduced, and higher device yields can be realized.