The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2015
Filed:
Jun. 10, 2011
Yoshitaka Sasago, Tokyo, JP;
Masaharu Kinoshita, Tokyo, JP;
Akira Kotabe, Tokyo, JP;
Takashi Kobayashi, Tokyo, JP;
Yoshitaka Sasago, Tokyo, JP;
Masaharu Kinoshita, Tokyo, JP;
Akira Kotabe, Tokyo, JP;
Takashi Kobayashi, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines () and bit lines () are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile