The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2015

Filed:

Mar. 31, 2009
Applicants:

Yefim-haim Fefer, Petah-Tikva, IL;

Sergey Sofer, Reshon Letzion, IL;

Boris Zapesochini, Jerusalem, IL;

Inventors:

Yefim-Haim Fefer, Petah-Tikva, IL;

Sergey Sofer, Reshon Letzion, IL;

Boris Zapesochini, Jerusalem, IL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/04 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2853 (2013.01); G01R 31/2884 (2013.01); G01R 31/31717 (2013.01);
Abstract

An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.


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