Fractional-n phase locked loop, operation method thereof, and devices having the same

Abstract

A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.