The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Feb. 05, 2014
Applicant:

Fujitsu Semiconductor Limited, Yokohama, Kanagawa, JP;

Inventor:

Yuichi Itonaga, Obu, JP;

Assignee:

SOCIONEXT INC., Yokohoma, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00 (2013.01); H03K 19/00361 (2013.01);
Abstract

An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power source and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power source and the output node; a first capacitive coupling part connected between a gate of the first PMOS transistor and gates of the second PMOS transistor and the second NMOS transistor; and a second capacitive coupling part connected between a gate of the first NMOS transistor and gates of the second NMOS transistor and the second PMOS transistor, a first bias voltage is applied to the gate terminal of the second PMOS transistor, and a second bias voltage is applied to the gate terminal of the second NMOS transistor.


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