The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Nov. 15, 2013
Applicant:

Mie Fujitsu Semiconductor Limited, Kuwana, JP;

Inventors:

David A. Kidd, San Jose, CA (US);

Edward J. Boling, Fremont, CA (US);

Vineet Agrawal, San Jose, CA (US);

Samuel Leshner, Los Gatos, CA (US);

Augustine Kuo, Berkeley, CA (US);

Sang-Soo Lee, Cupertino, CA (US);

Chao-Wu Chen, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/12 (2006.01); H03K 3/351 (2006.01);
U.S. Cl.
CPC ...
H03K 3/351 (2013.01);
Abstract

An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.


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