The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Sep. 28, 2012
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Christopher M. Gorman, Galway, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 5/00 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01);
Abstract

A differential level shifter includes: a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node; a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and a shift component coupled between the first output node and the second output node.


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