The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Jul. 09, 2013
Applicant:
Epistar Corporation, Hsinchu, TW;
Inventors:
De Shan Kuo, Hsinchu, TW;
Tsun Kai Ko, Hsinchu, TW;
Assignee:
EPISTAR CORPORATION, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/30 (2010.01); H01L 31/0352 (2006.01); H01L 33/12 (2010.01); H01L 33/10 (2010.01); H01L 33/14 (2010.01); H01L 51/52 (2006.01);
U.S. Cl.
CPC ...
H01L 33/30 (2013.01); H01L 31/035227 (2013.01); H01L 33/007 (2013.01); H01L 33/0062 (2013.01); H01L 33/12 (2013.01); H01L 33/10 (2013.01); H01L 33/145 (2013.01); H01L 51/5275 (2013.01); H01S 2304/12 (2013.01);
Abstract
An optoelectronic device comprises: a substrate having a first surface and a normal direction perpendicular to the first surface; a first semiconductor formed on the first surface of the substrate, comprising a plurality of hollow components formed in the first semiconductor layer; a first protection layer formed on a sidewall and a bottom wall of the plurality of the hollow components, and the bottom wall comprises a portion of the first surface; and a buffer layer formed on the first semiconductor layer wherein the buffer layer comprises a first surface and a second surface opposite to the first surface.