The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 28, 2015
Filed:
Jun. 26, 2012
Karl L. Erickson, Rochester, MN (US);
Phil C. Paone, Rochester, MN (US);
David P. Paulsen, Dodge Center, MN (US);
John E. Sheets, Ii, Zumbrota, MN (US);
Gregory J. Uhlmann, Rochester, MN (US);
Kelly L. Williams, Rochester, MN (US);
Karl L. Erickson, Rochester, MN (US);
Phil C. Paone, Rochester, MN (US);
David P. Paulsen, Dodge Center, MN (US);
John E. Sheets, II, Zumbrota, MN (US);
Gregory J. Uhlmann, Rochester, MN (US);
Kelly L. Williams, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.