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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9093323 B1

PDFFull Text
Date of Patent:
Jul. 28, 2015

Filed:

Jul. 15, 2013

Methods for selectively coating three-dimensional features on a substrate

Applicant:

Solexel, Inc., Milpitas, CA (US);

Inventors:

David Xuan-Qi Wang, Fremont, CA (US);

Mehrdad M. Moslehi, Los Altos, CA (US);

Somnath Nag, Saratoga, CA (US);

Assignee:

Solexel, Inc., Milpitas, CA (US);

Attorney:

John Wood

Primary Examiner:

Nadine Norton

Assistant Examiner:

Maki Angadi

Int. Cl.
CPC ...
B44C 1/22 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 31/0352 (2006.01); H01L 31/18 (2006.01); H01L 31/20 (2006.01); H05K 3/04 (2006.01); H05K 3/12 (2006.01); H01L 21/02 (2006.01); H05K 1/02 (2006.01); H05K 3/20 (2006.01); H01L 31/046 (2014.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 21/02617 (2013.01); H01L 21/6715 (2013.01); H01L 31/035281 (2013.01); H01L 31/1872 (2013.01); H01L 31/202 (2013.01); H05K 3/046 (2013.01); H05K 3/1258 (2013.01); H01L 31/046 (2014.12); H05K 1/0284 (2013.01); H05K 3/207 (2013.01); H05K 2201/09036 (2013.01); H05K 2201/09045 (2013.01); H05K 2203/0126 (2013.01); H05K 2203/0528 (2013.01); H05K 2203/308 (2013.01); Y02E 10/50 (2013.01);
Abstract

Methods here disclosed provide for selectively coating three-dimensional features on a substrate while avoiding liquid coating material wicking into micro cavities on the substrates. The steps include depositing a semiconductor layer on a sacrificial layer formed on a template and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating three-dimensional features on the substrate using a liquid coating step for applying a liquid coating material to a pre-determined surface of the three-dimensional features on the substrate.

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