The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Mar. 12, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Teruo Takagiwa, Kanagawa, JP;

Masatsugu Ogawa, Kanagawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array; a first data latch; a second data latch; a first data bus; a second data bus; a first temporary latch; a second temporary latch; and a control unit. The first and the second data latches are electrically connected to the memory cell array. The first data bus is electrically connected to the first data latch. The second data bus is electrically connected to the second data latch. The first temporary latch is electrically connected to the first data bus. The second temporary latch is electrically connected to the second data bus. The control unit is configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch.


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