The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Mar. 15, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Glenn D. Gilda, Binghamton, NY (US);

Mark R. Hodges, Endicott, NY (US);

Vesselina K. Papazova, Highland, NY (US);

Patrick J. Meaney, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/08 (2006.01);
U.S. Cl.
CPC ...
G06F 11/073 (2013.01); G06F 11/08 (2013.01);
Abstract

Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.


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