The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Dec. 15, 2009
Applicants:

Martin Taillefer, Redmond, WA (US);

Jan Gray, Bellevue, WA (US);

Richard Wurdack, Seattle, WA (US);

Gad Sheaffer, Haifa, IL;

Ali-reza Adl Tabatabai, San Jose, CA (US);

Inventors:

Martin Taillefer, Redmond, WA (US);

Jan Gray, Bellevue, WA (US);

Richard Wurdack, Seattle, WA (US);

Gad Sheaffer, Haifa, IL;

Ali-Reza Adl Tabatabai, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/46 (2006.01); G06F 11/36 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 9/467 (2013.01); G06F 11/3466 (2013.01); G06F 11/3612 (2013.01); G06F 11/3636 (2013.01); G06F 11/3648 (2013.01); G06F 11/3409 (2013.01); G06F 2201/86 (2013.01); G06F 2201/87 (2013.01); G06F 2201/88 (2013.01); G06F 2201/885 (2013.01);
Abstract

Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.


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