The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Feb. 22, 2011
Applicants:

Richard Roy Grisenthwaite, Nr Royston, GB;

David James Seal, Cherry Hinton, GB;

Inventors:

Richard Roy Grisenthwaite, Nr Royston, GB;

David James Seal, Cherry Hinton, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30112 (2013.01); G06F 9/30123 (2013.01); G06F 9/30138 (2013.01); G06F 9/30174 (2013.01); G06F 9/30189 (2013.01); G06F 9/30196 (2013.01); G06F 9/384 (2013.01); G06F 9/3863 (2013.01);
Abstract

A processoris provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.


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