The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9090004 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 28, 2015

Filed:

Feb. 06, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joseph Kuczynski, Rochester, MN (US);

Amanda E. Mikhail, Rochester, MN (US);

Arden L. Moore, Cedar Park, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/427 (2006.01); B29C 47/00 (2006.01); H01L 23/373 (2006.01); H01L 23/42 (2006.01); H01L 25/065 (2006.01); B29C 47/10 (2006.01); B29C 47/40 (2006.01); H01L 23/00 (2006.01); B29K 105/16 (2006.01);
U.S. Cl.
CPC ...
B29C 47/0057 (2013.01); B29C 47/1045 (2013.01); B29C 47/402 (2013.01); H01L 23/373 (2013.01); H01L 23/3737 (2013.01); H01L 23/42 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); B29K 2105/162 (2013.01); B29K 2995/0013 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29393 (2013.01); H01L 2224/29499 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/8385 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for enhancing internal layer-layer thermal interface performance and a chip stack of semiconductor chips using the method. The method includes adding a thermosetting polymer to the thermal interface material, dispersing a plurality of nanofibers into the thermal interface material, and un-crosslinking the thermosetting polymer in the thermal interface material. The method further includes extruding the thermal interface material through a die to orient the conductive axis of the nanofibers and polymer chains in the desired direction, and re-crosslinking the thermosetting polymer in the thermal interface material. The chip stack includes a first chip with circuitry on a first side, a second chip coupled to the first chip by a grid of connectors, and a thermal interface material pad between the chips. The thermal interface includes nanofibers and a polymer that allows for optimal alignment of the nanofibers and polymer chains.


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