The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Sep. 08, 2014
Applicant:
Lockheed Martin Corporation, Bethesda, MD (US);
Inventors:
Victoria Tabuena Pereira, Morrestown, NJ (US);
Lloyd Frederick Linder, Agoura Hills, CA (US);
Douglas A. Robl, Philadelphia, PA (US);
Brandon R. Davis, Mount Laurel, NJ (US);
Toshi Omori, Manlius, NY (US);
Assignee:
Lockheed Martin Corporation, Bethesda, MD (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/06 (2006.01); H03L 7/10 (2006.01); H03L 1/02 (2006.01); H03L 7/107 (2006.01); H03L 7/081 (2006.01); H03L 7/089 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0624 (2013.01); H03L 1/026 (2013.01); H03L 7/104 (2013.01); H03L 7/1077 (2013.01); G11C 27/026 (2013.01); H03L 7/0812 (2013.01); H03L 7/0814 (2013.01); H03L 7/0895 (2013.01); H03L 2207/04 (2013.01); H03M 1/12 (2013.01);
Abstract
A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.