The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Jan. 21, 2013
Applicant:

Agency for Science, Technology and Research, Singapore, SG;

Inventors:

Xinpeng Wang, Singapore, SG;

Xiang Li, Singapore, SG;

Navab Singh, Singapore, SG;

Guo-Qiang Patrick Lo, Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 45/04 (2013.01); H01L 27/2409 (2013.01); H01L 27/2454 (2013.01); H01L 45/1226 (2013.01); H01L 45/1253 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); Y10S 977/762 (2013.01); Y10S 977/943 (2013.01);
Abstract

According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.


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