The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Mar. 05, 2014
Applicant:
Peregrine Semiconductor Corporation, San Diego, CA (US);
Inventors:
Christopher N. Brindle, Poway, CA (US);
Jie Deng, South Burlington, VT (US);
Alper Genc, San Diego, CA (US);
Chieh-Kai Yang, Poway, CA (US);
Assignee:
Peregrine Semiconductor Corporation, San Diego, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7841 (2013.01); H01L 29/0688 (2013.01); H01L 29/36 (2013.01); H01L 29/78609 (2013.01); H01L 29/78615 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H03K 2217/0018 (2013.01); H03K 2217/0054 (2013.01);
Abstract
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.