The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Aug. 15, 2011
Applicant:
Simon Jonathan Stacey, Cambridgeshire, GB;
Inventor:
Simon Jonathan Stacey, Cambridgeshire, GB;
Assignee:
Cambridge Silicon Radio Limited, Cambridge, GB;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H05K 1/03 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 23/3142 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 23/3157 (2013.01); H01L 24/13 (2013.01); H01L 2224/0235 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05011 (2013.01); H01L 2224/05012 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/0519 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/13111 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01051 (2013.01);
Abstract
An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.