The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Jan. 30, 2013
Applicants:

Choong-ho Lee, Yongin-si, KR;

Donggu Yi, Seoul, KR;

Seung Chul Lee, Seongnam-si, KR;

Hyungsuk Lee, Suwon-si, KR;

Seonah Nam, Seoul, KR;

Changwoo OH, Suwon-si, KR;

Jongwook Lee, Yongin-si, KR;

Song-yi Han, Hwaseong-si, KR;

Inventors:

Choong-Ho Lee, Yongin-si, KR;

Donggu Yi, Seoul, KR;

Seung Chul Lee, Seongnam-si, KR;

Hyungsuk Lee, Suwon-si, KR;

Seonah Nam, Seoul, KR;

Changwoo Oh, Suwon-si, KR;

Jongwook Lee, Yongin-si, KR;

Song-Yi Han, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.


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