The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Nov. 22, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Jong-Pil Son, Seongnam-si, KR;

Uk-Song Kang, Seongnam-si, KR;

Chul-Woo Park, Yongin-si, KR;

Young-Soo Sohn, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 29/44 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 5/04 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/1048 (2013.01); G11C 29/808 (2013.01); G11C 5/04 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract

In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.


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