The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Aug. 05, 2011
Applicants:

Kuo-chang Su, Hsin-Chu, TW;

Yung-chih Chen, Hsin-Chu, TW;

Yu-chung Yang, Hsin-Chu, TW;

Chih-ying Lin, Hsin-Chu, TW;

Inventors:

Kuo-Chang Su, Hsin-Chu, TW;

Yung-Chih Chen, Hsin-Chu, TW;

Yu-Chung Yang, Hsin-Chu, TW;

Chih-Ying Lin, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORP., Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); G09G 3/3659 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0447 (2013.01); G09G 2330/023 (2013.01);
Abstract

The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout.


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