The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Sep. 06, 2012
Applicants:

Ryotaro Azuma, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Yoshikazu Katoh, Osaka, JP;

Inventors:

Ryotaro Azuma, Osaka, JP;

Kazuhiko Shimakawa, Osaka, JP;

Yoshikazu Katoh, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0088 (2013.01);
Abstract

A cross point variable nonvolatile memory device includes a memory cell array including: first memory cells (e.g., part of a memory cell array) having a common word line; and second memory cells (e.g., another part of the memory cell array or a compensation cell unit). When a predetermined memory cell among the first memory cells is written to by changing the predetermined memory cell to a first resistance state, a word line write circuit supplies a first voltage or a first current to a selected word line, a first bit line write circuit supplies a third voltage or a third current to one bit line of the first memory cells, and a second bit line write circuit supplies the third voltage or the third current to A bit line or lines of the second memory cells.


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