The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Jan. 28, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Wenqing Wu, San Diego, CA (US);

Venkatasubramanian Narayanan, San Diego, CA (US);

Kendrick Hoy Leong Yuen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/1673 (2013.01); G11C 2013/0042 (2013.01); G11C 2013/0057 (2013.01);
Abstract

Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems are disclosed. In one embodiment, sense amplifier is provided. The sense amplifier comprises a differential sense input coupled to bit line. The sense amplifier also comprises a differential reference input coupled to reference line. First inverter inverts first inverter input into first inverter output coupled to second inverter input of second inverter, first inverter output configured to provide state of bitcell. Second inverter inverts second inverter input into second inverter output coupled to first inverter input. Control circuit couples differential reference input to first inverter and differential sense input to second inverter in latch mode, and decouples differential reference input to first inverter and differential sense input to second inverter in sensing mode to provide sensed state of bitcell on first inverter output.


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