The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Oct. 22, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Dong-Hak Shin, Hwaseong-si, KR;

Yong-Sang Park, Seooul, KR;

Young-Yong Byun, Seoul, KR;

In-Chul Jeong, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); G11C 11/4099 (2013.01);
Abstract

A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.


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