The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Apr. 28, 2014
Applicant:

Rocketick Technologies Ltd., Ramat Gan, IL;

Inventors:

Uri Tal, Netanya, IL;

Shay Mizrachi, Hod-Hasharon, IL;

Tomer Ben-David, Yavne, IL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5022 (2013.01); G06F 8/45 (2013.01);
Abstract

A method for design simulation includes partitioning a verification task of a design () into a first plurality of atomic Processing Elements (PEs-) having execution dependencies (), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (), which includes a second plurality of processors () operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.


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