The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Jan. 05, 2012
Applicants:

Steven S. Thomson, San Diego, CA (US);

Mriganka Mondal, San Diego, CA (US);

Nishant Hariharan, San Diego, CA (US);

Inventors:

Steven S. Thomson, San Diego, CA (US);

Mriganka Mondal, San Diego, CA (US);

Nishant Hariharan, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 15/16 (2006.01); H04L 29/08 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/324 (2013.01); G06F 1/3228 (2013.01); G06F 1/3206 (2013.01); G06F 9/3885 (2013.01); H04L 67/10 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1285 (2013.01);
Abstract

Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently.


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